`include "include.v"

// 762.939453 Hz
`define CLK_PER 1310.72

module tb_seg7 ();

reg clk;
reg rst_n;
reg set;
reg [3:0] seg_in;
reg [1:0] anode_in;

wire [3:0] anode_out;
wire [6:0] seg_out;
reg  [3:0] anode_dec;

integer i;

always #(`CLK_PER/2) clk = ~clk;

initial begin
`ifndef IVERILOG
  $vcdpluson(tb_seg7);
`else
  $dumpfile("tb_seg7.vcd");
  $dumpvars(0,tb_seg7);
`endif
end

initial begin

  $display("tb_seg7.v starting. Clock period = %g us.", `CLK_PER); 

  $display(" SEG_0 = 0x%02X", `SEG_0);
  $display(" SEG_1 = 0x%02X", `SEG_1);
  $display(" SEG_2 = 0x%02X", `SEG_2);
  $display(" SEG_3 = 0x%02X", `SEG_3);
  $display(" SEG_4 = 0x%02X", `SEG_4);
  $display(" SEG_5 = 0x%02X", `SEG_5);
  $display(" SEG_6 = 0x%02X", `SEG_6);
  $display(" SEG_7 = 0x%02X", `SEG_7);
  $display(" SEG_8 = 0x%02X", `SEG_8);
  $display(" SEG_9 = 0x%02X", `SEG_9);
  $display(" SEG_A = 0x%02X", `SEG_A);
  $display(" SEG_B = 0x%02X", `SEG_B);
  $display(" SEG_C = 0x%02X", `SEG_C);
  $display(" SEG_D = 0x%02X", `SEG_D);
  $display(" SEG_E = 0x%02X", `SEG_E);
  $display(" SEG_F = 0x%02X", `SEG_F);


  clk = 1'b0;
  rst_n = 1'b0;
  set = 1'b0;
  seg_in = 4'b0;
  anode_in = 4'b0;

  @(posedge clk);
  @(posedge clk);
  rst_n = 1'b1;

  for (i = 32'b0; i < 32'd64; i = i + 1) begin
    @(negedge clk);
    {anode_in, seg_in} = i[6:0];
    set = 1'b1;
    @(negedge clk);
    set = 1'b0;
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
  end

  $finish;
end

always @(*) begin
  seg_decode(anode_out, seg_out);
end

always @(*) begin
  anode_decode(anode_out);
end

seg7_top i_seg7_top (
  .clk(clk),
  .rst_n(rst_n),
  .set(set),
  .seg_in(seg_in),
  .anode_in(anode_in),
  .anode_out(anode_out),
  .seg_out(seg_out),
  .dp(dp)
);

task seg_decode;
  input [3:0] anode_out;
  input [6:0] seg_out;
begin
  case (seg_out)
  `SEG_0 : $display("0 on anode %h @%t ns", anode_dec, $time);
  `SEG_1 : $display("1 on anode %h @%t ns", anode_dec, $time);
  `SEG_2 : $display("2 on anode %h @%t ns", anode_dec, $time);
  `SEG_3 : $display("3 on anode %h @%t ns", anode_dec, $time);
  `SEG_4 : $display("4 on anode %h @%t ns", anode_dec, $time);
  `SEG_5 : $display("5 on anode %h @%t ns", anode_dec, $time);
  `SEG_6 : $display("6 on anode %h @%t ns", anode_dec, $time);
  `SEG_7 : $display("7 on anode %h @%t ns", anode_dec, $time);
  `SEG_8 : $display("8 on anode %h @%t ns", anode_dec, $time);
  `SEG_9 : $display("9 on anode %h @%t ns", anode_dec, $time);
  `SEG_A : $display("A on anode %h @%t ns", anode_dec, $time);
  `SEG_B : $display("B on anode %h @%t ns", anode_dec, $time);
  `SEG_C : $display("C on anode %h @%t ns", anode_dec, $time);
  `SEG_D : $display("D on anode %h @%t ns", anode_dec, $time);
  `SEG_E : $display("E on anode %h @%t ns", anode_dec, $time);
  `SEG_F : $display("F on anode %h @%t ns", anode_dec, $time);
  default: $display("ERROR - seg = %07b anode = %h @%t ns", seg_out, anode_dec, $time);
  endcase
end
endtask

task anode_decode;
  input  [3:0] anode_out;
begin
  case (anode_out)
  `AN_1   : anode_dec = 3'h1;
  `AN_2   : anode_dec = 3'h2;
  `AN_3   : anode_dec = 3'h3;
  `AN_4   : anode_dec = 3'h4;
  default : anode_dec = 3'hX;
  endcase
end
endtask

endmodule
